1. Technical Field
The invention relates generally to semiconductor fabrication, and more particularly, to structures and a method for grounding front-end-of-line (FEOL) structures, such as a gate stack or active region, through a silicon-on-insulator (SOI) substrate.
2. Background Art
In-line voltage contrast (VC) inspection is a powerful technique for detecting and isolating yield limiting defects in the semiconductor fabricating industry. In-line VC inspection includes scanning the wafer surface in which test structures exist with a scanning electron microscope (SEM). As the inspection proceeds, the SEM induces a charge on all electrically floating elements whereas any grounded elements remain at a zero potential. This potential difference is visible to the SEM. In particular, for electron landing energies less than the second crossover of the secondary electron yield curve (approximately 1.5 keV for tungsten (W) and copper (Cu)), grounded elements appear bright whereas floating elements appear dark.
Test structures exploiting this phenomenon can be created for many yield limiting defects including metal, gate and active region shorts and opens, and via and contact opens. For example, FIGS. 1A-B, show a short (FIG. 1B) indicated by a normally floating (dark) element becoming bright, and an open (FIG. 1A) indicated when a normally bright element becomes dark. As shown, even if the defect causing the electrical failure is buried or extremely small, its existence is indicated by a change in the VC signal of the entire element. In addition, the exact location of an open is indicated by a change in the VC signal of the structure after the break.
A number of challenges exist relative to building VC test structures. One challenge is grounding front-end-of-line (FEOL) structures targeting the active region or gate stack levels, especially for silicon-on-insulator (SOI) technology. For bulk silicon technology, an active region may be grounded to the substrate by doping the active region P+, while masking out the N well so that the P+ directly contacts the P− material of the substrate. However, with SOI technology, the buried oxide (BOX) layer presents an additional barrier so the above-described grounding technique does not work. Some SOI technologies provide a mask level for forming holes through the BOX layer. Design rules typically do not allow this level and the active region or gate stack levels to be coincident. However, this level enables the first metal level to make contact to the substrate. Since the active region and gate stack levels also can be connected to the first metal level, they may be grounded through as shown in FIG. 2. Unfortunately this ground path is not helpful for VC inspection for active region and gate stack structures because the ground path to the VC test structure is required when the test structure is still exposed at the wafer surface and visible to the SEM. Therefore, VC test structures that require grounding of an active region are currently impossible for SOI technology.
Several approaches exist to ground polysilicon structures in SOI substrates. For example, Patterson et al., “Rapid Reduction of Poly-Silicon Electrical D0 using uLoop Test Structures,” Proceedings of ASMC, pp. 266-272, March 2003, describes the use of a modified process flow for generating grounded gate stack VC test structures. This short loop sequence starts with the formation of a 2000 angstrom (Å) silicon dioxide (SiO2) layer. Contact holes are patterned in the silicon dioxide (SiO2). The contacts are opened with an isotropic etch. The gate stack excluding the gate dielectric (e.g., SiO2) is then deposited. Gate stack VC test structures are then formed using the contact holes to ground select elements. This method has a number of disadvantages. First, special short loop wafers are necessary, which creates an additional cost. Second, because the transistors will not work, very little other data can be collected for comparison. Third, the process sequence is not entirely representative of the real process.
A second technique to ground gate stack structures in SOI technology is to use large capacitors to generate a virtual ground path. This technique also suffers from a number of drawbacks. First, these capacitors are formed with a plate of gate stack over the active region, and take up a large amount of the area (e.g., approximately 25-40% of a test area). Secondly, a large plate of gate stack is often a design rule violation. A third technique for grounding the gate stack level is through the first metal layer, as described earlier. Again, this method is not useful for VC inspection because the ground path to the VC test structures is required when the test structures are still exposed at the wafer surface. By the first metal level, the test structures have been covered by the contact dielectric.
In view of the foregoing, there is a need in the art for a solution to the problems of the related art.